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  The EM428M1644RTA is a high speed synchronous graphic RAM fabricated with ultra High performance CMOS process containing 134,217,728 bits which organized as2meg word x  4 Banks x 16bits. The 128Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and it transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at the I /O pins.
Available packages:TSOPII 66P 400mil.
 
Feature
Internal Double-data-rate architecture with 2 accesses per clock cycle
VDD/VDDQ = 2.5V +/- for (-75and -6)
VDD/VDDQ = 2.5V +/- for (-5)
  Burst length of 2,4,8
2.5V SSTL-2 compatible I/O
2,2.5,3 clock read latency
Bi-directional, intermittent data strobe(DQS)
All inputs except data and DM are sampled at the positive edge of the system clock
Data Mask (DM) for write data.
Auto & self refresh supported
4K Refresh cycle / 64ms
Sequential & Interleaved burst type available
Auto Precharge option for each burst-accesses
DQS edge-aligned with data for read cycles
DQS center-aligned with data for write cycles
DLL aligns DQ & DQS transitions with CLK's
Auto refresh and self refresh
4,096 refresh cycles / 64ms
DataSheet
Timing
 
 
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