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The EM48BM0884VTA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 8Meg words x 4 banks by 8 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL. Available packages: TSOPII 54P 400mil.
 
Feature
Fully synchronous to positive clock edge
Single 3.3V +/- 0.3V power supply
LVTTL compatible with multiplexed address
Programmable Burst Length (B/L) - 1,2,4,8 or full page
Programmable CAS Latency (C/L) - 3
Data Mask (DQM) for Read / Write masking
Programmable wrap sequence - Sequential (B/L = 1/2/4/8/full page )
　 - Interleave (B/L = 1/2/4/8 )
Burst read with single-bit write operation
All inputs are sampled at the rising edge of the system clock
Auto refresh and self refresh
8,192 refresh cycles / 64ms
DataSheet
Timing
 
　
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