Feature |
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JEDEC Standard VDD/VDDQ = 1.5V ±
0.075V. |
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All inputs and outputs are
compatible with SSTL_15 interface. |
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Fully differential clock
inputs (CK,/CK) operation. |
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8 banks |
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Posted CAS by programmable additive
latency |
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Bust length: 4 with Burst Chop (BC) and
8. |
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CAS Write Latency (CWL): 5, 6, 7, 8 |
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CAS Latency (CL): 6, 7, 8, 9, 10, 11 |
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Write Latency (WL) =Read Latency (RL)
-1. |
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Bi-directional Differential
Data Strobe (DQS) |
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Data inputs on DQS centers
when write. |
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Data outputs on DQS, /DQS edges when read. |
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On chip DLL align DQ, DQS and
/DQS transition with CK transition. |
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DM mask write data-in at the
both rising and falling edges of the data strobe. |
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Sequential & Interleaved Burst type
available both for 8 & 4 with BC. |
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Multi Purpose Register (MPR) for
pre-defined pattern read out |
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On Die Termination (ODT) options:
Synchronous ODT, Dynamic ODT, and Asynchronous ODT |
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Auto refresh and self refresh. |
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8,192 Refresh Cycles / 64ms . |
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Refresh Interval: 7.8us T case
between 0°C
~ 85°C |
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Refresh Interval: 3.9us T case
between 85°C
~ 95°C |
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RoHS Compliance |
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Driver Strength: RZQ/7, RZQ/6,RZQ/5(RZQ=240 Ω) |
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High Temperature Self-Refresh rate
enable |
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Multi Purpose Register for pre-defined
pattern read out |
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ZQ calibration for DQ drive and ODT |
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RESET pin for initialization and reset
function |