Home-> DRAM -> EM44DM0888LBA  


DRAM products

EOREX™ DRAM products includes

Mobile SDRAM












Click to download datasheet regarding. Please note that the content of datasheet is subject to change without notice.


The EM44DM0888LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1,073,741,824 bits which organized as 16Mbits x 8 banks by 8 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 800 Mb/sec/pin (DDR2-800) for general applications.

The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR2 devices operates with a single power supply: 1.8V 0.1V VDD and VDDQ. Available package: TFBGA-60Ball (with 0.8mm x 0.8mm ball pitch)


JEDEC standard VDD/VDDQ = 1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface.
Fully differential clock inputs (CK,/CK) operation.
8 banks
Posted CAS
Burst Length:4 and 8
Programmable CAS latency (CL): 7, 6
Programmable Additive Latency (AL):0, 1 , 2, 3, 4, 5 & 6.
Write Latency (WL) = READ Latency (RL)-1.

Read Data Strobe (RDQS) supported

Bi-directional Differential Data Strobe (DQS)
Data inputs on DQS centers when write.
Data outputs on DQS, /DQS edges when read.
On chip DLL align DQ, DQS and /DQS transition with CK transition.
DM mask write data-in at the both rising and falling edges of the data strobe.
Sequential & interleaved burst type available.
Off-Chip Driver (OCD) impedance adjustment.
On Die Termination (ODT)
  Auto refresh and self refresh.

8,192 Refresh Cycles / 64ms.


Refresh Interval: 7.8us Tcase between 0C ~ 85C

  Partial Array Self-Refresh (PASR)
  RoHS Compliance

tRAS lockout supported

  High Temperature self-refresh rate enable
Copyright 2008 Eorex Corporation. Terms and conditions