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The EM44BM1684LBB is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 8Mbits x 4 banks by 16 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 800 Mb/sec/pin (DDR2-800) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 512 Mb DDR2 devices operate with a single power supply: 1.8V 0.1V VDD and VDDQ. Available package:TFBGA-84Ball.

 

 
Feature
JEDEC standard VDD/VDDQ = 1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface.
Fully differential clock inputs (CK,/CK) operation.
4 banks
Posted CAS
Burst Length:4 and 8
Programmable CAS latency (CL): 3, 4, 5, 6 and 7.
Programmable Additive Latency (AL):0, 1 , 2, 3, 4, 5 and 6.
Writed Latency (WL) = READ Latency (RL)-1.
Read Latency (RL)= Programmable Additive Latency (AL)+ CAS Latency (CL)
Bi-directional Differential Data Strobe (DQS)
Data inputs on DQS centers when write.
Data outputs on DQS, /DQS edges when read.
On chip DLL align DQ, DQS and /DQS transition with CK transition.
DM mask write data-in at the both rising and falling edges of the data strobe.
Sequential & interleaved burst type available.
Off-Chip Driver (OCD) impedance adjustment.
On Die Termination (ODT)
  Auto refresh and self refresh.
 

8,192 Refresh Cycles / 64ms.

  Average refresh period 7.8us at lower than Tcase 85, 3.9us at 85℃<Tcase≦95
  Partial Array Self-Refresh (PASR)
  RoHS Compliance
  High Temperature self-refresh rate enable
DataSheet
Timing
 
 
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