Feature |
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Internal Double-data-rate architecture with
2 accesses per clock cycle |
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1.8V+/-0.1V VDD/VDDQ |
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1.8V LV-COMS compatible I/O. |
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Burst length (B/L) of 2,4,8,16 |
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3 Clock read latency |
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Bi-directional,intermittent data
strobe(DQS) |
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All inputs except data and DM are
sampled at the positive edge of the system clock. |
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Data Mask (DM) for write data |
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Sequential & Interleaved Burst type
available |
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Auto Precharge option for each burst
accesses |
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DQS edge-aligned with data for Read
cycles |
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DQS center-aligned with data for Write
cycles |
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No DLL ;CK to DQS is not synchronized
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Deep power down mode |
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Partial Array Self-Refresh(PASR) |
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Auto Temperature Compensated
Self-Refresh (TCSR) by built-in temperature sensor
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Auto Refresh and Self Refresh |
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8,192 Refresh Cycles / 64ms |
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