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The EM42AM1684RTC is high speed Synchronous
graphic RAM fabricated with ultra high performance CMOS process
containing 268,435,456 bits which organized as 4Meg words x 4
banks by 16 bits. The 256Mb DDR SDRAM uses a double data rate
architecture to accomplish high-speed operation. The data path
internally prefetches multiple bits and transfers the data for
both rising and falling edges of the system clock. It means the
doubled data bandwidth can be achieved at the I/O pins.
Available package: TSOPII 66P 400mil.
Internal Double-Date-Rate architecture
with twice accesses per clock cycle
2.5V SSTL-2 compatible I/O
Burst length of 2,4,8
2.5,3 clock read latency
Bi-directional, intermittent data strobe (DQS)
All inputs except data and DM are sampled
at the positive edge of the system clock
Data Mask (DM) for write data.
Sequential & Interleaved burst
Auto Precharge option for each burst-accesses
DQS edge-aligned with data for read cycles
DQS center-aligned with data for write cycles
DLL aligns DQ & DQS transitions with CLK